1. Field of the Invention
This invention relates generally to a container system for storing and transporting of sensitive components such as semiconductor chips, and, more particularly, to a component carrier that provides an improved physically protective environment for the components during storage and shipping.
2. Discussion of the Related Art
Semiconductor devices typically comprise one or more semiconductor chips designed for performing a desired function. The manufacture of semiconductor devices begins with the manufacture of the semiconductor chips. The semiconductor chips are first produced in a wafer form and subsequently diced from the wafer into individual chips. The individual chips are then packaged on a suitable substrate. During the device manufacturing process, the semiconductor chips are usually stored temporarily in a chip carrier and transported from one processing station to the next with the chip carrier. At the time the semiconductor chips are stored and transported, the semiconductor chips may include, on a top surface thereof, die having wire bond pads or solder balls suitable for Controlled Collapsed Chip Connector (C4). The semiconductor chips are hereinafter referred to as wire bond die product and bumped die product, respectively.
Referring to FIG. 1, a semiconductor component 10 includes a semiconductor chip 12 mounted upon a substrate or package 14 as shown. The example shown is a bumped die product 12 connected to a substrate or package 14 having input/output pins 16 for connection with a next level of packaging, such as a printed circuit board (not shown). For connecting the chip 12 to the substrate 14, the semiconductor chip 12 is appropriately placed upon the substrate 14 and then together, the chip and substrate are subjected to a reflow process. FIG. 2 exemplifies a cross sectional view of the semiconductor chip properly joined to the underlying substrate via solder ball connection after a solder reflow process. In the properly joined chip and substrate of FIG. 2, electrical connections are made in the form of solder columns 18. In contrast, FIG. 3 exemplifies a cross sectional view of the semiconductor chip improperly joined to the underlying substrate. The electrical connections of the chip 12 to substrate 14 of FIG. 3 are not all properly made. For instance, numeral 20 identifies a nonwet or poor solder joint, which is susceptible to failure subsequent to completion of the device manufacturing process, and further corresponds to a high reliability exposure. In addition, numeral 22 identifies an open solder connection resulting from a low volume C4 solder ball pad, further corresponding to a yield exposure. The low volume C4 solder ball pad may have been caused as a result of a good solder ball having been damaged during a previous handling, storage, and/or transportation of the semiconductor die during the manufacturing process.
In the semiconductor device manufacturing process, chip container systems are used, such as are known in the art. A first example of a known chip container system 30 including chip carriers 32 is shown in FIGS. 4A-4C. In short, semiconductor die product are placed upon individual chip carriers 32, in appropriate pockets or segmented rows 34, and a plurality of chip carriers 32 loaded with chips are stacked one upon another in a stacked arrangement. The semiconductor die product or chip typically has a thickness on the order of two-thirds (2/3) of the total pocket depth. Chip carriers are stacked by process requirement. The underside bottom surface 36 of one chip carrier is used to cover a top of an underlying adjacent chip carrier. In the chip container system 30 of FIGS. 4A-4C, the underlying bottom surface 36 of a chip carrier 32 includes a fine textured flat surface or similar sand blast type finish. Such a fine textured flat surface is used on the covering surface for both wire bond and bumped die product for preventing the die product from sticking thereto. Unfortunately, the textured flat surface becomes smoothed out, by repeated uses and cleaning, over a period of time. A smoothed out covering surface is undesirable and problematic, since a wire bond die product is subject to sticking thereto due to surface tension. In a second container system design 40 having chip carriers 42 as shown in FIGS. 5A-5C, a cross grid finish has been used on a bottom surface 46 of a chip carrier. The cross grid finish is undesirable and problematic in the case of bumped die product, since bumped die product are highly subject to damage thereby. Both wire bond and bumped die product should stick to a bottom surface of the chip carrier in the appropriate pocket or segmented row (34 of FIG. 4C, 44 of FIG. 5C) during a carrier shipment to reduce chip movement within the carrier, further for reducing damage to the die product edges. However, while both wire bond and bumped die product should stick to the bottom surface of the appropriate pocket or segmented row of the chip carrier during a carrier shipment, die product sticking to an underside of an adjacent chip carrier causes lost chips and/or damage in follow-on processing and follow-on process tooling. Again, the fine textured flat surface is undesirable since it possesses an early wear/failure rate due to repeated use and cleaning, thereby causing a relapse of the underside surface tension problem.
It would thus be desirable to eliminate undesired die product sticking, surface tension, adhesion problems to an underside of an adjacent chip carrier of a stack of chip carriers for wire bond die products and simultaneously reduce damaging bumped die products caused by an underside of the adjacent chip carrier of a stack of chip carriers.